1. Field of the Invention
The present invention relates to a gate electrode in a semiconductor device with improved Gate Oxide Integration (GOI) characteristics and in which spike formation has been suppressed.
The present invention also relates to formation of metal wiring in a semiconductor device and, more particularly, to a method for forming a gate electrode in a semiconductor device which can improve GOI characteristics and effectively suppress spike formation.
2. Background of the Related Art
A related art method for forming metal wiring will be explained with reference to the attached drawings. FIGS. 1a to 1g illustrate the steps of a related art method for forming a gate electrode.
Referring to FIG. 1a, a gate insulating film 3 is formed on the surface of a semiconductor substrate 1 having an active region defined thereon by a field oxide film 2 grown to a thickness of 60 xc3x85 by thermal oxidation. Then, a 1000 xc3x85-thick doped polysilicon layer 4 is formed on the gate insulating film 3 and field oxide film 2 by Low Pressure Chemical Vapor Deposition (LPCVD). An HF solution is then used to remove oxides on the surface of the doped polysilicon layer 4.
Then, as shown in FIG. 1b, a 100 xc3x85-thick TiN layer 5 and a 1000 xc3x85-thick TiSix layer 6 are formed by sputtering and, as shown in FIG. 1c, subjected to annealing at a temperature ranging from 800 to 900xc2x0 C. for 30 minutes under an Ar or N2 atmosphere. The annealing transforms the TiSix layer 6 from the C49 phase, which has a high resistivity, into the C54 phase, thereby dropping the resistivity below 20 xcexcxcexa9/cm.
As shown in FIG. 1d, a first insulating layer 7 is formed to a thickness of 2500 xc3x85 on the TiSix layer 6. As shown in FIG. 1e, a stack of the first insulating layer 7, the TiSix layer 6, the TiN layer 5, the doped polysilicon layer 4 and the gate insulating film 3 are selectively patterned to form a gate electrode 8.
Referring to FIG. 1f, a 500 xc3x85-thick second insulating film (not shown) is formed on the entire exposed surface, including the gate electrode 8, and is etched back to form gate sidewalls 9 at both sides of the gate electrode 8. As shown in FIG. 1g, the gate electrode 8, inclusive of the gate sidewalls 9, is used as a mask in conducting impurity ion injection and diffusion to form source/drain regions 10. In this related art method for forming metal wiring in a semiconductor device, the Si/Ti ratio selected for sputtering the TiSix layer 6 is between 2.1 and 2.3, in order to drop the resistivity and to reduce particle formation during deposition.
However, this related art method for forming metal wiring in a semiconductor device has the following problem:
Subsequent re-oxidation, that eliminates the damage done to the gate insulating film 3 during patterning of the gate electrode 8, forms TiSix spikes in the doped polysilicon layer 4 due to diffusion of Ti through grain boundaries of the doped polysilicon layer 4. Si from the doped polysilicon layer 4 is consumed during the re-oxidation, causing rapid deterioration of gate line resistance and GOI characteristics. In order to prevent this, a Ti polycide of a TiSix/TiN/poly-Si structure is suggested. However, because the TiN in the TiSix/TiN/poly-Si is susceptible to oxidation, TiSix/TiOx/poly-Si forms after the re-oxidation. As a result, contact resistance between the TiSix layer 6 and poly-Si layer 4 increases and GOI characteristics drop sharply. Thus, an effective application of re-oxidation to the related art method for forming metal wiring in a semiconductor device is impeded.
Accordingly, the present invention is directed to a method for forming a gate electrode in a semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for forming a gate electrode in a semiconductor device which can improve GOI characteristics and that allows an effective suppression of spike formation.
Additional features and advantages of the present invention will be set forth in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the present invention. The objectives and other advantages of the present invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as in the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the method for forming a gate electrode in a semiconductor device includes the steps of: forming a gate insulating film over a semiconductor substrate, forming a first semiconductor layer over the gate insulating film, forming a barrier layer over the first semiconductor layer to prevent formation of metal silicide spikes in the first semiconductor layer, forming a second semiconductor layer over the barrier layer, and forming a metal silicide layer over the second semiconductor layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.